At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1. Role Overview & Objective We are looking for a motivated SRAM Circuit Design Engineer to
Summary The Lead PERC Rule Developer will drive PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability-related verification. The role requires strong hands-on expertise in Calibre LVS/PERC, CMOS and FinFET fundamentals,
Job ID 520656 Posted since 02-Sep-2026 Organization Digital Industries Field of work Research & Development Company SIEMENS EDA (INDIA) PRIVATE LIMITED Experience level Experienced Professional Job type Full-time Work mode Office/Site only Employment type Permanent Location(s)
Job ID 520657 Posted since 02-Sep-2026 Organization Digital Industries Field of work Research & Development Company SIEMENS EDA (INDIA) PRIVATE LIMITED Experience level Early Professional Job type Full-time Work mode Office/Site only Employment type Permanent Location(s)
Job Summary We are looking for a skilled Physical Design Engineer to support end-to-end ASIC/SoC implementation from netlist/RTL to GDSII. The engineer will be responsible for physical implementation, timing closure, PPA optimization, physical verification, and sign-off
A Senior DFT (Design-for-Test) Engineer is responsible for architecting, implementing, and validating test methodologies in complex SoC/ASIC designs, ensuring manufacturability, reliability, and efficient silicon bring-up. The role blends deep technical expertise in scan insertion, ATPG, MBIST,
About Multiscale AI Multiscale AI provides AI Agents and Digital Twins for Semiconductor Manufacturing. With offices in Atlanta, San Francisco, and Hyderabad, we help semiconductor manufacturers optimize fabs and achieve measurable results. The Role Were building