General Information Job Title Senior Verification Manager - IP Development Job ID 13453 Country India City Noida Date Posted 15-Nov-2025 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No Descriptions & Requirements
Join our Team About This Opportunity We are looking for an experienced Problem Manager to lead end-to-end problem management activities for the IP Core and Mobile Packet Backbone Network (MPBN) domain. The ideal candidate should have strong
Join our Team About this opportunity This Role is responsible for Alarm analysis, Operation-maintenance, trouble-shooting & Change Request Implementation on IP nodes (like Routers ,switches ,firewalls, load balancers and security gateways etc). Also responsible for Trouble Ticket
Join our Team About this opportunity This Role is responsible for Alarm analysis, Operation-maintenance, trouble-shooting & Change Request Implementation on IP nodes (like Routers ,switches ,firewalls, load balancers and security gateways etc). Also responsible for Trouble Ticket
Join our Team About this opportunity: Join Ericsson as a Network Engineer to leverage your technical knowledge for the analysis, audit, design, and optimization of our advanced telecom networks. This vital role spans across various domains,
Join our Team About this opportunity To work as an IP security engineer responsible for implementing, configuring, and troubleshooting Checkpoint, Fortinet, Cisco ASA firewalls, and F5 LTM/AFM, ensuring optimal security and performance. What you will do •
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create
Join our Team About this opportunity This Role is responsible for Alarm analysis, Operation-maintenance, trouble-shooting & Change Request Implementation on IP nodes (like Routers ,switches ,firewalls, load balancers and security gateways etc). Also responsible for Trouble Ticket
Join our Team About this opportunity This Role is responsible for Alarm analysis, Operation-maintenance, trouble-shooting & Change Request Implementation on IP nodes (like Routers ,switches ,firewalls, load balancers and security gateways etc). Also responsible for Trouble Ticket
Times Network is loking for a Lead for the North India revenue charter for our flagship IPs across TimesNow.in, ETNow.in, Digit.in, Times Drive, and Pickleball. Key Responsibilities: Own and deliver revenue targets for the North region. Build
In This Role, Your Responsibilities Will Be: Hardware Engineering Leadership Lead hardware engineering for DCS projects: architecture, cabinet design, I/O distribution, marshalling philosophy, network layout, and 3rd party interfaces. Define deliverables, plan execution, allocate work to
You Are You find clarity in complexity and know that good documentation is about what engineers can actually use when solving a problem, not just what looks complete. Writing energizes you, but so does understanding how
Summary: We are looking for Experienced Analog Mixed-Signal Layout Engineer with 3–7 years of expertise in PLL, Oscillator, Data Converter, Power Management, and IO IP layouts across advanced technology nodes (5nm–40nm). Strong proficiency in Cadence Virtuoso, analog
In this Role, Your Responsibilities Will Be: Site walk-downs for data collection and I/O database preparation, database partitioning from Third Party DCS / PLC systems Design and implementation of power plant controls and protection Systems Process
We are looking for a Patent Search Senior Analyst to join our IP Search Team in Noida. This is a an opportunity to support Fortune 100 companies on various phases in IP Life cycle management. The team member
We are looking for an Associate Trademark Watch Analyst to join our highly regarded Global Trademark team at Clarivate, Noida. This is an amazing opportunity to work with a global team which is required for successful
Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation and
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write
Senior Operations Analyst WHAT MAKES US, US Join some of the most innovative thinkers in FinTech as we lead the evolution of financial technology. If you are an innovative, curious, collaborative person who embraces challenges and
KPMG entities in India are professional services firm(s). These Indian member firms are affiliated with KPMG International Limited. KPMG was established in India in August 1993. Our professionals leverage the global network of firms, and are