Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to
General Information Job Title SOC Engineering, Principal Engineer (DFT) Job ID 18085 Country India City Noida Date Posted 30-Jun-2026 Job Category Engineering Job Subcategory SOC Engineering Hire Type Employee Remote Eligible No Descriptions & Requirements Job Description
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create
Director SoC Design Business Line Description We are part of MCU/MPU Engineering, a central design organization within NXP, developing products for multiple business lines in Automotive, Internet of Things (IoT), Networking, and Radio Frequency products, with
This role is for one of the Weekdays clients Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA) Min Experience: 3 years Location: NCR, Bengaluru, Hyderabad JobType: full-time We are looking for
Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and