We are looking for a Principal HW DFT Engineer who will architect, implement, and validate NXP’s Automotive grade products. You will be responsible for advanced test strategies and implementation, verification and validation of pre/post tapeout of DFT features,
Summary : We are looking for an experienced and highly motivated DFT Lead Engineer with strong expertise in Design-for-Test methodologies for complex SoC/ASIC designs. The ideal candidate should have hands-on experience in Scan Insertion, ATPG, MBIST, LBIST,
Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to
General Information Job Title Staff R&D Prototyping Engineer, Test Solutions Job ID 17515 Country India City Noida Date Posted 15-May-2026 Job Category Engineering Job Subcategory R&D Engineering Hire Type Employee Remote Eligible No Descriptions & Requirements
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
This role is for one of the Weekdays clients Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA) Min Experience: 3 years Location: NCR, Bengaluru, Hyderabad JobType: full-time We are looking for
Description : Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services...
Job Description Experience: 5+ years Role Summary We are seeking skilled Physical Design Engineer with exposure of physical design cycle including Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on performing
Job Description Experience: 7-10 years Role Summary We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis
Job Description SoC Architecture & Integration Lead integration of complex multi-billion transistor SoCs comprising CPUs, GPUs, NPUs, AI accelerators, memory subsystems, and high-speed peripherals. Define and implement scalable SoC architectures, subsystem partitioning, and integration strategies. Drive
Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position: Sr. Principal Software Engineer Grade: T5 Experience: 12- 16 Years Location: Bangalore/Noida Job Responsibilities: R&D
Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and