Primary and Secondary Responsibilities: Develop unique and sometimes complex bench characterization test methodologies for ADC,DAC,PLL,USB, VREG, OSC,DDR, LOW POWER and IO PADs in order to determine and verify the device’s functional and electrical performance across Manufacturing
OUR STORY At STMicroelectronics, we believe in the power of technology to drive innovation and make a positive impact on people, businesses, and society. As a global semiconductor company, our advanced technologies and chips form the hidden
Job Summary The Functional Safety Architect plays a key role in defining, analyzing, and validating safety concepts and architectures across embedded hardware and software systems. This role focuses on developing safety requirements, performing analyses, supporting implementation
Generic Job Description (not Job Level specific): The Design Methodologies and Tools Engineer / Architect develops and applies Computer Aided Design (CAD) software engineering methods, theories and research techniques in the investigation and solution of technical
Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation
Principal Engineer - Digital IP Verification (G4) Role Overview We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The
Job Summary We are seeking a CAD Engineer specializing in Digital Verification to build, enhance, and support scalable verification infrastructure, methodologies, and EDA automation flows for ASIC/SoC development. The role focuses on enabling verification teams with
Digital IP Verification Engineers [10 to 15 yrs exp] Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex Vision / Image Processing IPs
Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation
• Master/Bachelors Degree in Electrical/Electronic Engineering • Experience 6-10 Years in high performance digital logic designs and SoC Integration using ARM Cores, Bus Protocols and Interconnects • Building Subsystems and/or SoC RTL integration • LINT/CDC/RDC signoffs
Generic Job Description (not Job Level specific): The Digital Physical Design Engineer / Architect is responsible for a physical implementation of IP, Subsystem or IC design. The individual is responsible from RTL synthesis to GDS implementation
Role Overview We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The role demands deep expertise in advanced verification
Principal Engineer - Digital IP Verification (G4) Role Overview We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs. The
Digital IP Verification Engineers [7 to 13 yrs exp] Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced
Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributor driving roadmaps for Vision IP domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex Vision IPs solutions. Working closely with experienced
Senior Principal Engineer - Digital IP Verification (G5) Role Overview We are seeking a highly motivated, technically strong, and execution-focused Individual Contributor to lead and deliver first-pass success for complex Digital IP and Subsystem verification programs.
Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual Contributor willing to go deeper into logic design and take the challenge of architecting and developing Complex IPs / Subsystems using the latest advanced Design flow methodologies and
Job Opportunity: Seeking highly motivated, energetic, team-oriented person driving roadmaps for IP / Subsystem domain including complete IP portfolio, going deeper into logic design and architecting and developing Complex IPs / Subsystems solutions. Working closely with
Digital IP Verification Engineers [14 to 20 yrs exp] Job Opportunity: Seeking highly motivated, energetic, team-oriented Individual contributor willing to take the challenge of delivering the first pass success of complex IPs using the latest advanced
Senior Emulation Engineer – VELOCE / ZEBU / Palladium (Automotive SoC) NXP is looking for a STAFF‑level Emulation Engineer with 5–10 years of hands‑on experience in SoC emulation to work on cutting‑edge automotive MCUs/SoCs. This role