Static Timing Analysis Jobs In India - 764 Job Positions Available

Role: STA Engineer Job Description Key Responsibilities: Develop, review, and maintain robust SDC constraints (clocks, I/O, generated clocks, timing exceptions). Perform block‑level and full‑chip STA using PrimeTime/Tempus and ensure timing closure across all MMMC scenarios. Own RTL synthesis

Static Timing Analysis (STA) Engineer Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design

Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. As a STA

Position Overview We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely

Static Timing Analysis (STA) Engineer Job Description JD:3 Experience : 3+ years of relevant experience Expectations: Candidate should have strong STA fundamentals. Has done timing sign-off including timing margin calculations independently on SoC level. Experience in handling STA of multi-power domain

We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or full‑chip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks , along with

Introduction At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security,

Position Overview We are seeking an experienced STA Lead with strong expertise in Static Timing Analysis for complex ASIC/SoC designs. The ideal candidate will be responsible for driving timing closure activities across block and full-chip level designs while collaborating closely

Introduction At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security,

Job Details Job Description: The Role and Impact: As a Physical Design Timing Engineer, you will play a pivotal role in advancing Intels next-generation SoCs by ensuring their optimal performance and efficiency. Your expertise will directly impact

We are seeking an experienced STA Lead with strong expertise in ASIC timing analysis and timing closure across block and/or fullchip designs. The role requires deep understanding of STA methodologies, constraints, ECO flows, and signoff checks , along with

About SiFive As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world.