About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell,
Job Description: Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation. Hands on experience in ICC and primetime. Block level implementation from netlist to GDS. Handling timing closure
Job Description: Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation. Hands on experience in ICC and primetime. Block level implementation from netlist to GDS. Handling timing closure
Job Details: Job Description: Experience with owning the full chip/Block level and taping out multiple complex SoCs.Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc. Full-Chip/Block
Job Details: Job Description: Experience with owning the full chip/Block level and taping out multiple complex SoCs.Hands-on experience with industry standard Cadence or Synopsys tool suite, and other Sign-off tools from Siemens (Mentor), Ansys etc. Full-Chip/Block
About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell,
Job Description: Chip level floorplanning, partitioning, timing budget generations, power planning, top PnR, CTS, block integration and ECO generation. Hands on experience in ICC and primetime. Block level implementation from netlist to GDS. Handling timing closure
Job Details: Job Description: We are looking for Physical Design Engineer with strong RTL2GDS Skills. This role responsibilities include Synthesis, Floor-planning, Place and Route, Timing Analysis, Convergence, IR/EM analysis, Formal verification, VCLP, DRC/LVS clean-up and delivery of the Blocks
Job Details: Job Description: Design Enablement team at India, is part of Technology Development group, having charter to develop methodology for advance process nodes, providing opportunity, to be among the first one to work on latest technology.
Job Details: Job Description: Senior Physical Design Engineer with strong RTL2GDS skills with Proven track record of implementing designs through Logic synthesis, floorplanning, place and route, Excellent understanding on different types of CTS implementation, extraction & Timing closure techniques. Make
Key Responsibilities Would be responsible for hands-on physical implementation core platforms and SoCs. Evaluate and deploy the evolving physical design methodologies to handle increasingly complex SoC/IP designs within aggressive, market-driven schedules Active participation in benchmarking of library, technology parameters, implementation
5 to 10 years relevant experience Lead with experience in SoC Physical design across multiple technology nodes including 5nm for TSMC & Other foundries. Excellent hands-on P&R skills with expert knowledge in ICC/Innovus Expert knowledge in all aspects
proteanTecs is a dynamic fast-paced start-up company, transforming the way reliability of electronics is achieved. In a world where machines are gaining immense responsibility over our lives, sudden failure is not an option. We have developed
Working on latest Synopsys Implementation Technologies (Physical Synthesis, Multi Source CTS, Floor-planning etc.) to solve complex PPA Challenges. Working on developing and deploying full platform flows and methodologies for advanced nodes by collaborating with key stake holders.
Job Details: Job Description: We are looking for Physical Design Engineers with strong RTL2GDSii Skill. Job responsibilities include Logic Synthesis, Floor-planning, Place and Route, Timing Analysis, Convergence, IR/EM analysis, Formal verification, VC-LP, DRC/LVS clean-up and delivery of the Blocks
Experience with the block-level Experience in full chip-level Physical Design 8+years of experience with Innvous tool and less than 7nm technology experience....
Infinera is a global supplier of innovative networking solutions. Our customers include the leading service providers, data center operators, internet content providers (ICPs), cable operators, enterprises, and government agencies worldwide, including 9 of the top 10
Please find the JD Below: Senior Physical Design Engineer/ Lead Experience : 3+Years Location: Bangalore Skill: Physical Design 3+ year’s Experience in Physical Design engineering Experience serving as Senior physical design engineer or SOC or block coordinator or top level integrator in TSMC 12m or 16nm
Physical Design Engineers for ODC project: AIML Services Pvt Ltd is Hiring Physical Design engineers (Trained freshers & experienced engg/Leads) for ODC Projects based in Bangalore/Hyderabad. The physical design role in integrated circuit (IC) engineering involves transforming a logical design into a physical layout that can
Position Description: Exp: 4- 12 Yrs · Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure. · The candidate will have