Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: Interface with design team to ensure DFT design rules and coverages are met. Generating high quality manufacturing ATPG test patterns for stuck-at (SAF), transition
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: We are seeking a highly motivated and technically strong Staff Engineer, Silicon & Data Automation Systems to help build and expand a growing
Summary : We are looking for an experienced and highly motivated DFT Lead Engineer with strong expertise in Design-for-Test methodologies for complex SoC/ASIC designs. The ideal candidate should have hands-on experience in Scan Insertion, ATPG, MBIST, LBIST,
Job Details: Job Description: Client Engineering Group in Intel is responsible for delivering Complex SoC solutions for desktop and mobile segments. We are looking for an energetic, passionate and process oriented DFx engineers who has extensive
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: Job Description As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create
Job Details: Job Description: Key Responsibilities:Leadership and Management:-Manage and technically guide a high-performing DFT team focused on X86 CPU DFT design and validation.-Develop detailed execution plans for parallel activities across multiple projects and ensure timely, high-quality delivery.DFT Design and
Job Description : Core DFT skills considered for this position should include some of the following: Scan compression and insertion, Memory BIST and repair scheme implementation, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate level
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create
About the Team The Chip Methodology & Automation (CMA) team within Arm’s Solutions Engineering organization develops scalable methodologies, flows, and automation that enable efficient deployment of Arm-based SoCs across internal teams, customers, and ecosystem partners. The
Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to
Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan
Introduction At IBM Infrastructure & Technology, we design and operate the systems that keep the world running. From high-resiliency mainframes and hybrid cloud platforms to networking, automation, and site reliability. Our teams ensure the performance, security,
This role is for one of the Weekdays clients Min Experience: 3+ years Location: Hyderabad JobType: full-time We are looking for a skilled and detail-oriented DFT Engineer to join our semiconductor design team in Hyderabad. This role
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Prior 7-12 years of professional experience in SoC/ASIC Digital Design with focus on Design for Test
Senior DFT Engineer: You will be responsible for designing, implementing, and verifying DFT architectures for complex SoCs. You will work closely with RTL, physical design, and verification teams to ensure robust testability and high-quality silicon. Key Responsibilities -Define
General Information Job Title DFT Solutions Engineer Job ID 17640 Country India City Bengaluru Date Posted 26-May-2026 Job Category Engineering Job Subcategory Solutions Engineering Hire Type Employee Remote Eligible No Descriptions & Requirements Job Description and Requirements
General Information Job Title Solutions Engineering, Sr Staff Engineer (DFT, RTL Design product Engineer) Job ID 17017 Country India City Bengaluru Date Posted 16-Apr-2026 Job Category Engineering Job Subcategory Solutions Engineering Hire Type Employee Remote Eligible No
Minimum qualifications: PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering or related technical field, or equivalent practical experience. Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools. Preferred qualifications: 2 years