General Information Job Title Staff Interface IP Verification Engineer (Pre-Silicon) Job ID 18379 Country India City Bengaluru Date Posted 13-Aug-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No Descriptions &
Schaeffler is a dynamic global technology company and its success has been a result of its entrepreneurial spirit and long history of private ownership. Does that sound interesting to you? As a partner to all of
General Information Job Title Senior Staff Interface IP Verification Engineer (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Job ID 18400 Country India City Bengaluru Date Posted 17-Aug-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No
General Information Job Title Senior Staff- Interface IP Verification (Pre-Silicon- PCIe/CXL/DDR/Ethernet) Job ID 18424 Country India City Bengaluru Date Posted 19-Aug-2026 Job Category Engineering Job Subcategory ASIC Digital Design Hire Type Employee Remote Eligible No Descriptions
This role is for one of Weekday’s clients Salary range: Rs 1000000 - Rs 9000000 (ie INR 10 - 90 LPA) Min Experience: 7+ years Location: Bengaluru JobType: full-time We are seeking an experienced Staff Engineer
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: This position is for RTL designer role in DSP processor team. The position involves in-depth understanding of the ASIC design flow from RTL
Exp: 3- 6 years Location: Bangalore Notice Period: Immediate to 30 days Description of the Role: Requirement for a qualified FPGA Firmware Engineer to perform Design and Development activities. The engineer will work on various project
ASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design, RTL coding, and ASIC development. The ideal candidate will have extensive experience in designing, developing, and optimizing high-performance
Job Title: DFT Engineer Experience Level: 2+ years Location: Hyderabad and Banglaore Job Description: Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs. Insert and verify scan chains (scan insertion, ATPG, scan stitching).
Job Title: Lead FPGA Design Engineer Experience Required: 7–12 years Location: Hyderabad/Bangalore Job Type: Full-time Industry: Semiconductor / Electronics / Embedded Systems Job Summary: We are looking for a highly skilled and experienced Lead FPGA Design
Job Summary: We are seeking a highly motivated RTL Design Engineer with 7-10 years of experience to join our growing team. You will play a vital role in the design and development of complex digital logic
Design Verification Engineer Company: PQAngels Technologies Pvt. Ltd. PQAngels Technologies is looking for an experienced Design Verification Engineer to join our VLSI/semiconductor engineering team. The ideal candidate will have strong hands-on experience in SystemVerilog, UVM, Verilog,
Job Title: Design Verification Lead Location: Bangalore/Hyderabad Experience: 7+yrs Job Type: Full-time Industry: Semiconductors / VLSI / EDA Education: B.E./B.Tech or M.E./M.Tech in ECE/EEE or related field Job Description: We are looking for a passionate and
FPGA Design Engineer We are seeking an RTL FPGA Engineer with a strong background in FPGA design, RTL development, and digital system design. The ideal candidate will have expertise in developing FPGA solutions using VHDL or
Experience: 5 Years Location: Bangalore/Hyderabad Education: B.E/B.Tech in ECE/EEE or M.E/M.Tech in VLSI/Electronics Roles and Responsibilities DDR Verification: Lead the verification of DDR memory controller and PHY designs, ensuring compliance with DDR standards such as DDR3,
Job Title: FPGA RTL Design Engineer Location: Bengaluru, India Experience: 4+ Years Role Overview: We are seeking a skilled FPGA RTL Design Engineer with 4+ years of experience in FPGA development and digital design. The candidate
Design Verification Engineer - Senior / Lead / Sr. Lead Location: Bangalore / Hyderabad Experience: 4 to 10 Years Required Qualifications: Bachelor’s or Master’s degree in Electrical Engineering , Computer Engineering , or a related field.
Job Title: DFT Engineer Experience Level: 2 years Location: Hyderabad and Banglaore Job Description: Key Responsibilities: Develop and implement DFT architecture and methodologies for ASIC/SoC designs. Insert and verify scan chains (scan insertion, ATPG, scan stitching).