Design for Test (DFT) Engineer (Experienced) We are looking for an experienced DFT Engineer with strong expertise in scan, ATPG, and test methodologies for complex digital designs. The candidate will be responsible for implementing and validating DFT architectures to ensure high
The Digital Physical Design Engineer is responsible for complete STA signoff for the SOC or Subsystem. The individual is responsible for writing timing constraints, interacting with the counterpart functions, such as Frontend, DFT and IP to write correct
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of whats possible to enable next-generation experiences and drives digital transformation to help create
This role is for one of the Weekdays clients Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA) Min Experience: 3 years Location: NCR, Bengaluru, Hyderabad JobType: full-time We are looking for
• Computer Science with at least 4-6 years of relevant industry experience • Solid understanding of PCIe protocol and the validation of PCIe interfaces or any high-speed IO; ethernet performance is an added advantage. • Experience
Description : Location: IN-KA-Bangalore, India (eInfochips) Time Type: Full time Job Category: Engineering Services...
Job Summary Position: Sr. Design Engineer 1 Experience: 4+ relevant experience. Location - India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of
Job Summary Position: Sr. Design Engineer 2- DFT Experience: 6+ relevant experience. Location - India Education: B.Tech/M.Tech To be successful in this role you will: Seeking highly motivated, energetic, team-oriented Individual contributors willing to take the challenge of
Description Cadence Design Systems is looking for a highly motivated software and hardware engineer to work as a member of the R&D staff on Cadence’s MODUS DFT software solution. MODUS is a complete product that encompasses Design for
Job Description Experience: 7-10 years Role Summary We are seeking an experienced Physical Design Engineer with strong debug skills in Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on RTL synthesis ownership,
Job Description Experience: 5+ years Role Summary We are seeking skilled Physical Design Engineer with exposure of physical design cycle including Synthesis, UPF, VCLP, LEC to join our semiconductor backend team. The role focuses on performing RTL
Job Description SoC Architecture & Integration Lead integration of complex multi-billion transistor SoCs comprising CPUs, GPUs, NPUs, AI accelerators, memory subsystems, and high-speed peripherals. Define and implement scalable SoC architectures, subsystem partitioning, and integration strategies. Drive
Job Description Collaborate with system architects and micro-architects to define high-level, implementable SoC specifications. Own end-to-end SOC RTL delivery while analysing and optimizing design for power, performance, and area (PPA) targets. Influence SoC definition, features, and
Job Description Emulation Engineer (Location: Noida) Experince: 10-20 Years Job Description ( Location: NOIDA) We are seeking a diligent Emulation leader to join our team at Renesas. Responsibilities include enhancing build/debug emulation methodology and flows, develop capabilities
Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and