Layout in advanced CMOS technologies including floorplan, placement, routing, DRC, LVS etc. Expertise on 2nm ,3nm, 5nm,7nm,14nm etc. technology nodes on various analog mixed signal blocks such as HBM, PLL, Band gap, LDO, ADC, DAC, SERDES,
SRAM Layout Engineer Experience:- 5-15 years Qualifications:- B.Tech/B.E/M.Tech/M.E Location:-Bangalore Role and Responsibilities:- Experienced SRAM layout profiles who can work and design SRAM leafcells, Compiler level LVS/DRC independently. Skill Requirements:- SRAM layout compiler development. Good to have:-
RTL Design Verification Engineer Experience- 3+ years Location-Bangalore NP- 0- 15 days Key Responsibilities Functional Verification Develop and execute RTL verification plans based on design specifications and system requirements. Build, enhance, and maintain System Verilog /