Job Description: Derive sensor-based system level specifications and the circuit architecture ASIC design and tapeout Coordinate with the fab (interact with chip Manufacturing lab team on the PDK (process design kit), ESD (for I/Os) and other
RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
RTL Design Engineer (SDC Constraints) : + : : / We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise
Technical Lead - Design Verification Experience: 8+ Years Location: Bengaluru We are seeking a highly skilled and experienced Senior Design Verification Engineer to join our SoC/ASIC verification team in Bangalore. The ideal candidate will have a
AMS Verification Engineer Experience: 3 to 5 Years Location: Bangalore Job Description Perform Analog Mixed-Signal (AMS) verification using SystemVerilog, Wreal, and Verilog-AMS for IP and subsystem-level designs. Develop and maintain mixed-signal testbenches , behavioral and real-number
As an AMS Design & Analog Layout Engineer at HCLTech, you will play a pivotal role in designing, developing, and validating advanced analog and mixed-signal (AMS) integrated circuits. Your contributions will directly impact the development of
Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a
NoC Verification Engineer Experience : 7 to 14 Years Key Responsibilities: Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. Define and implement test plans, coverage models, scoreboards, monitors, and
Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology
Senior Staff DFT Engineer Location: Bengaluru Experience: 12–16 Years Role Overview We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.
Memory Layout Engineer Experience: 4–8 years Location – Bangalore Qualifications: Bachelors or Masters degree in Electrical Engineering, Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes Key Skills & Responsibilities: Hands-on experience in layout
Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers
IT Infrastructure System and EDA Tools Administration Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as a Lead for IT Infra and System and EDA Tool Management. Location : Bangalore,
Hiring: Synthesis Engineer | 5+ Years Location: Bengaluru Experience: 5+ Years Notice Period: 0–30 Days Education: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines Job Description: We are looking for an experienced Synthesis Engineer with strong
Lead STA Engineer Among. The top 4 IT companies, in India ranked by market capitalization and revenue Bangalore /Hyderabad/Kochi Role Overview As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing
Senior DFT Engineer – Automation & Scripting Experience: 3 to 5 Years Location: Bangalore Job Description: We are seeking a DFT Engineer with strong expertise in automation and scripting to support and enhance DFT flows across
Static Timing Analysis (STA) Engineer Experience: 3 to 6 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits
Lead Synthesis Engineer Location: Bengaluru, India Experience: 6–12 Years About the Role Were looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. Youll own synthesis convergence, optimize PPA,
Responsibilities As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify
IR/EM Low Power Design Engineer About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end