Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a
Job description (Staff/Senior Staff Engineer) Backend Integration Engineer Working experience on 7nm and below Technologies. Proficient in Physical Synthesis flow and PPA optimizations with emphasis on Timing and Low Power design. Proficient in Equivalence Checks, Low
Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology
AIML Pipeline / Dataflow Design Lead Location: Bangalore, India |Company: LTSCT — L&T Semiconductor Technologies Limited Reporting To: Senior Architect, DC HW Systems | Experience: 10+ years (mandatory) Role Summary We are hiring two AIML Pipeline
Educational Qualification B.E./B.Tech and M.E./M.Tech in CSE/IT or relevant specialization with First Class. Ph.D. in Computer Science & Engineering / Information Technology or allied discipline. Minimum 5 years of teaching, research, or industry experience, with post-Ph.D.
Senior Synthesis Engineer Experience Level :- 3yrs to 6yrs Notice Period :- Immediate to 45 Days Work Location :- Bangalore Job Description – Senior Synthesis Engineer (VLSI) Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in
Memory Layout Engineer Experience: 4–8 years Location – Bangalore Qualifications: Bachelors or Masters degree in Electrical Engineering, Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes Key Skills & Responsibilities: Hands-on experience in layout
SoC STA & Synthesis – Senior Engineer About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end
Hiring: Synthesis Engineer | 5+ Years Location: Bengaluru Experience: 5+ Years Notice Period: 0–30 Days Education: B.E./B.Tech/M.E./M.Tech in ECE, EEE, VLSI, or related disciplines Job Description: We are looking for an experienced Synthesis Engineer with strong
Experience : 3 to 8 years Location : Hyderabad/Noida Role and Responsibilities: Responsible for Memory Compiler layout development and verification.· Responsible for Layout design and development of Memory blocks such as Array, Row/ Column decoder, sense amplifier,
Analog Layout Engineer – Lower Node Job Description Position: Analog Layout Engineer Experience: 3-6 Years Location: Bangalore Notice Period: Immediate- 30 Days Key Responsibilities Design and develop analog/mixed-signal layouts for advanced technology nodes. Work on lower-node
Senior DFT Engineer – Automation & Scripting Experience: 3 to 5 Years Location: Bangalore Job Description: We are seeking a DFT Engineer with strong expertise in automation and scripting to support and enhance DFT flows across
Static Timing Analysis (STA) Engineer Experience: 3 to 6 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits
Below is the JD for RTL engineers. We need to build strong RTL team. Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience in Logic design/micro-architecture/RTL coding is a must.
Hi All, Job Location: Bangalore Notice Period: 15 days to 30 Days Minimum: 5+ Years 1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog. 2. Should have
Brief About Tech Mahindra – Silicon Engineering Tech Mahindra Silicon Engineering is a key part of Tech Mahindras semiconductor and engineering services portfolio, delivering end-to-end solutions across the silicon lifecycle for global semiconductor, automotive, consumer, and
Lead Static Timing Analysis (STA) Engineer Experience: 6 to 10 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated
We are looking for a Memory Design Engineer with 3+ years of experience in memory circuit design. The ideal candidate should have hands-on experience in designing and verifying SRAM/compiler memory circuits, along with a strong understanding of
Lead Synthesis Engineer Location: Bengaluru, India Experience: 6–12 Years About the Role Were looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. Youll own synthesis convergence, optimize PPA,