Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology nodes. As a STA
STA Design Engineer We need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience in Backend (Physical Design) STA at SoC level.
Static Timing Analysis (STA) Engineer Experience: 3 to 6 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves
Lead Static Timing Analysis (STA) Engineer Experience: 6 to 10 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role
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ASIC Design Engineer We are seeking a skilled ASIC Design Engineer with a solid background in digital design , RTL coding , and ASIC development . The ideal candidate will have extensive experience in designing, developing,
IR/EM Low Power Design Engineer About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end to back-end
Role Overview: The FPGA Technical Lead is responsible for driving the complete FPGA design lifecycle — from architecture definition to on-board validation — for complex digital and wireless communication systems. This role demands both strong technical
SoC STA & Synthesis – Senior Engineer About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Korea’s semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end
Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers
Lead STA Engineer Among. The top 4 IT companies, in India ranked by market capitalization and revenue Bangalore /Hyderabad/Kochi Role Overview As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing closure
Summary: We are seeking an innovative and highly motivated Digital Design Engineer to develop next-generation MCU and embedded processing platforms while leveraging AI/ML technologies to transform silicon development workflows. The candidate will contribute to RTL design,
Key Responsibilities: Develop and optimize logic design, register transfer level (RTL) coding, and simulation for the CPU. Participate in defining the architecture and microarchitecture features of the CPU design. Write RTL and optimize logic for power,