Exp level: 2 to 5 years Location: Bangalore Notice Period: Immediate joiners are preffered. Responsibilites: Design and implement analog layouts for high-performance circuits (e.g., amplifiers, ADCs, DACs, voltage regulators) using TSMC 3nm and 5nm nodes. Perform design
Position: Analog Layout Engineer Experience: 4+ Years Job Summary: We are seeking a highly motivated Analog Layout Engineer to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal
Company:Qualcomm India Private Limited Job Area:Engineering Group, Engineering Group Hardware Engineering General Summary: Minimum 5 years’ experience in a hands-on PDK role Expertise in Calibre/ICV runset coding for DRC/LVS/ERC/PERC/ESD/Latch-up/Antenna…. Experience with developing and customization of the
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Opportunity: Foundry PDK Design Enablement Engineer Experience Level: 2–4 Years Department: Methodology & Flow Enablement
Position: Analog Layout Engineer Experience: 4+ Years Job Summary: We are seeking a highly motivated Analog Layout Engineer to join our semiconductor design team. The candidate will be responsible for the physical implementation of high-performance analog and mixed-signal
Company Description Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering