Summary The Lead PERC Rule Developer will drive PERC methodology, rule development, and flow enablement for ESD, latch-up, power-domain, connectivity, and reliability-related verification. The role requires strong hands-on expertise in Calibre LVS/PERC, CMOS and FinFET fundamentals,
General Information Job Title Staff Engineer - Analog Design Job ID 18437 Country India City Noida Date Posted 21-Aug-2026 Job Category Engineering Job Subcategory Analog Design Hire Type Employee Remote Eligible No Descriptions & Requirements Job Description
Role Purpose The Physical IP Division in Arm Noida creates Memory IPs which are extensively used by thousands of SoC designers around the world to design leading edge chips. We are currently developing memory fast cache
We’re hiring at Pitney Bowes, where top talent builds meaningful careers and lasting impact. We Move fast, Deliver excellence, and Win together…that’s The Pitney Bowes way. Here, how we work matters just as much as what
Job Overview: The Physical IP Division in Arm develops Memory IPs which are extensively used by thousands of SoC designers around the world to build groundbreaking chips. We are currently developing memory fast cache instances on
Job Overview: The Physical IP Division in Arm creates Memory IPs which are extensively used by thousands of SoC designers around the world to design groundbreaking chips. We are currently developing memory fast cache instances on
Job Overview: The Physical IP Division in Arm creates Memory IPs which are extensively used by thousands of SoC designers around the world to design groundbreaking chips. We are currently developing memory fast cache instances on
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