Digital Design Engineer with hand on experience in Scan insertion, ATPG, GLS. He/She will be responsible for understanding the DFT architecture of the design and providing the scan insertion collaterals to the implementation team, to enable scan
This role is for one of the Weekdays clients Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA) Min Experience: 3 years Location: NCR, Bengaluru, Hyderabad JobType: full-time We are looking for
This role is for one of the Weekdays clients Salary range: Rs 700000 - Rs 2500000 (ie INR 7 - 25 LPA) Min Experience: 3 years Location: NCR, Bengaluru, Hyderabad JobType: full-time We are looking for
Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and