RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
Experience 3-6 years Role and responsibility: Ability to execute block level P&R and Timing closure activities. Will be responsible for owning up block level P&R. Perform Netlist2GDS on blocks Implementation of multimillion gate SoC designs in