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Synopsys Jobs In Thane, Maharashtra - 11 Job Positions Available

1 – 9 of 11 jobs

Job Description: Derive sensor-based system level specifications and the circuit architecture ASIC design and tapeout Coordinate with the fab (interact with chip Manufacturing lab team on the PDK (process design kit), ESD (for I/Os) and other

TIH | IIT Bombay  3 days ago

RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.

ACL Digital  27 days ago

RTL Design Engineer (SDC Constraints) : + : : / We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise

ALTEN Calsoft Labs  10 days ago

Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers

ACL Digital  2 days ago
LeadSoc Technologies Pvt Ltd jobs

Senior Staff DFT Engineer Location: Bengaluru Experience: 12–16 Years Role Overview We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.

LeadSoc Technologies Pvt Ltd  2 days ago
LeadSoc Technologies Pvt Ltd jobs

Lead Static Timing Analysis (STA) Engineer Experience: 6 to 10 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated

LeadSoc Technologies Pvt Ltd  2 days ago
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LeadSoc Technologies Pvt Ltd jobs

Lead Synthesis Engineer Location: Bengaluru, India Experience: 6–12 Years About the Role Were looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. Youll own synthesis convergence, optimize PPA,

LeadSoc Technologies Pvt Ltd  2 days ago
Tech Mahindra jobs

Memory Layout Engineer Experience: 4–8 years Location – Bangalore Qualifications: Bachelors or Masters degree in Electrical Engineering, Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes Key Skills & Responsibilities: Hands-on experience in layout

Tech Mahindra  2 days ago

STA Design Engineer We need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience in Backend (Physical Design) STA

Sevya Multimedia  2 days ago

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