Job Description: Derive sensor-based system level specifications and the circuit architecture ASIC design and tapeout Coordinate with the fab (interact with chip Manufacturing lab team on the PDK (process design kit), ESD (for I/Os) and other
RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
RTL Design Engineer (SDC Constraints) : + : : / We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints. The ideal candidate will have deep expertise
As an AMS Design & Analog Layout Engineer at HCLTech, you will play a pivotal role in designing, developing, and validating advanced analog and mixed-signal (AMS) integrated circuits. Your contributions will directly impact the development of
Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology
AMS Verification Engineer Experience: 3 to 5 Years Location: Bangalore Job Description Perform Analog Mixed-Signal (AMS) verification using SystemVerilog, Wreal, and Verilog-AMS for IP and subsystem-level designs. Develop and maintain mixed-signal testbenches , behavioral and real-number
Lead Design Engineer As an RTL Design Lead , you will play a critical role in leading the RTL design and verification process for complex digital designs . You will manage a team of RTL engineers
NoC Verification Engineer Experience : 7 to 14 Years Key Responsibilities: Develop UVM-based verification environments for NoC/IP blocks such as FlexNoC, GNOC, or custom NoC fabrics. Define and implement test plans, coverage models, scoreboards, monitors, and
Job Summary: We are seeking a highly accomplished Design for Testability (DFT) Engineer to join our elite team and lead the DFT efforts for our most critical ASIC and SoC projects. This senior-level position demands a
Senior Staff DFT Engineer Location: Bengaluru Experience: 12–16 Years Role Overview We are looking for a Senior Staff DFT Engineer with deep hands-on expertise in DFT architecture, implementation, ATPG and silicon bring-up for complex SoC designs.
Lead Static Timing Analysis (STA) Engineer Experience: 6 to 10 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated
Lead Synthesis Engineer Location: Bengaluru, India Experience: 6–12 Years About the Role Were looking for a Lead Synthesis Engineer to drive RTL-to-Gate implementation for complex SoCs across advanced technology nodes. Youll own synthesis convergence, optimize PPA,
Memory Layout Engineer Experience: 4–8 years Location – Bangalore Qualifications: Bachelors or Masters degree in Electrical Engineering, Technology Nodes: TSMC/Samsung – 2nm, 3nm, 5nm, 7nm, and GF nodes Key Skills & Responsibilities: Hands-on experience in layout
STA Design Engineer We need experienced Static Timing Analysis engineers to design and integrate an ARM/RISCV-based SoCs in cutting edge technology and with complex functionality. Skills: Overall 3+ years industry experience in Backend (Physical Design) STA