Quadric delivers its GPNPU as soft IP — RTL and implementation collateral — enabling customers to integrate our processor into their own SoCs across a range of process nodes and foundries. You will drive PPA optimization across
1) Expertise in Design, development of Embedded software. BSP, device drivers for Power Arch / ARM Arch processors and FPGAs 2) Person should have worked on Xilinx FPGAs. Must be familiar with board bring up, boot
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Cadence IP Tensilica group is a leading provider of configurable embedded processor technology, with a growing
This role sits at the core of a high-performance processor IP team, owning PPA optimization, building scalable RTL-to-GDSII flows, and supporting customers through integration and tapeout. You will work across architecture, RTL, and physical design to drive real
Quadric has created an innovative general purpose neural processing unit (GPNPU) architecture. Quadrics co-optimized software and hardware is targeted to run neural network (NN) inference workloads in a wide variety of edge and endpoint devices, ranging
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Responsibilities: The Candidate will have design responsibility, including floor planning, power grid design, place and
