RTL Design Engineer (SDC Constraints) ๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ: ๐ณ+ ๐ฌ๐ฒ๐ฎ๐ฟ๐ ๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: ๐๐ฎ๐ป๐ด๐ฎ๐น๐ผ๐ฟ๐ฒ ๐ช๐ผ๐ฟ๐ธ ๐ ๐ผ๐ฑ๐ฒ: ๐๐๐ฏ๐ฟ๐ถ๐ฑ / ๐ฅ๐ฒ๐บ๐ผ๐๐ฒ ๐๐ผ๐ฏ ๐ข๐๐ฒ๐ฟ๐๐ถ๐ฒ๐ We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
Job Description: Responsible for chip level STA convergence from early stages to signoff. Participate in top level floor plan and clock planning. IP & SoC timing constraints definition for all modes including DFT Constraints quality check
Job description (Staff/Senior Staff Engineer) Backend Integration Engineer Working experience on 7nm and below Technologies. Proficient in Physical Synthesis flow and PPA optimizations with emphasis on Timing and Low Power design. Proficient in Equivalence Checks, Low
Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology
SoC STA & Synthesis โ Senior Engineer About Semifive Founded in Seoul in 2019, SEMIFIVE is basing its foundation on Koreaโs semiconductor design competency that was amassed for more than 20 years. With expertise spanning front-end
STA Engineer KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure of GPU Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff
Senior Synthesis Engineer Experience Level :- 3yrs to 6yrs Notice Period :- Immediate to 45 Days Work Location :- Bangalore Job Description โ Senior Synthesis Engineer (VLSI) Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in
Lead STA Engineer Among. The top 4 IT companies, in India ranked by market capitalization and revenue Bangalore /Hyderabad/Kochi Role Overview As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing
Static Timing Analysis (STA) Engineer Experience: 3 to 6 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits
Lead Static Timing Analysis (STA) Engineer Experience: 6 to 10 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated
Below is the JD for RTL engineers. We need to build strong RTL team. Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience in Logic design/micro-architecture/RTL coding is a must.