RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
Lead STA Engineer Among. The top 4 IT companies, in India ranked by market capitalization and revenue Bangalore /Hyderabad/Kochi Role Overview As a Lead STA Engineer(preferably 11+Yrs Experience ), you will be responsible for ensuring timing
Senior Synthesis Engineer Experience Level :- 3yrs to 6yrs Notice Period :- Immediate to 45 Days Work Location :- Bangalore Job Description – Senior Synthesis Engineer (VLSI) Worked on 7nm/5nm/Future sub-micron Technologies. Hands on experience in
Job Description: Responsible for chip level STA convergence from early stages to signoff. Participate in top level floor plan and clock planning. IP & SoC timing constraints definition for all modes including DFT Constraints quality check
Static Timing Analysis (STA) Engineer Experience: 3 to 6 years of experience in STA. Location :- Bangalore Job Summary The Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits
Job description (Staff/Senior Staff Engineer) Backend Integration Engineer Working experience on 7nm and below Technologies. Proficient in Physical Synthesis flow and PPA optimizations with emphasis on Timing and Low Power design. Proficient in Equivalence Checks, Low
Below is the JD for RTL engineers. We need to build strong RTL team. Minimum 8+ years of work experience in ASIC RTL Design, Synthesis, STA & FV Experience in Logic design/micro-architecture/RTL coding is a must.
Static Timing Analysis (STA) Lead Join the India team of most cutting-edge and well-funded storage startup in Silicon Valley as the Lead STA Engineer working on timing closure of complex high performance ASIC in latest technology