DVS Jobs In Maharashtra - 26 Job Positions Available

L&T Technologies (LTTS) is hiring for Design Verification Engineers with 5+ Years of experience :: Job Location : Bangalore Please find the detailed job description below :: Experience in development of UVM based verification environments from

LTTS is hiring for Design Verification Engineers with 5+ Years of experience. Job Location : Bangalore, India Detailed JD is as below :: Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches

Lead the Analog Intelligence Inside Tomorrows Connected World At Texas Instruments , the chips enabling secure automotive access, industrial sensing, and medical monitoring start with world-class analog design. If youre a seasoned analog design leader with

Why This Role Rocks You’ll be executing media strategies that don’t just spend – they perform . From launching scroll-stopping campaigns to decoding what makes audiences click, you’ll be in the driver’s seat of performance-led media

Primary Responsibilities Project customer requirements into BOM, drawings, specifications, DFMEA etc. Design and develop steering column products that adhere to industry best practices and as per customer requirements. Design the steering column product keeping manufacturing and

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics

Job Description DV Positions: Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-stem/SoC level verification Develop functional tests based on verification test plan Drive Design Verification to closure based on defined verification metrics

Build Something Extraordinary — Lead AMS Verification for World-Class High Voltage Power ICs At Texas Instruments , our High Voltage Power (HVP) team develops some of the worlds most advanced power solutions — AC/DC controllers, isolated

Formal Verification Engineer Experience : 4 to 12 Years Location : Bangalore Job Description Responsible for developing and executing formal verification strategies for IP and SoC blocks. Write and prove assertions using SystemVerilog Assertions (SVA) or

Responsibilities As a Pune MCU team DFT lead, this candidate needs to architect DFT design, in charge of DFT instruments insertion and simulation; work with SOC lead/IP designers and DV team to deliver DFT implementations, verify and

LEAD BEHAVIORAL MODELING ENGINEER – LATTICE SEMICONDUCTOR INDIA Location: Hyderabad / Pune / Chennai (India) JOB SUMMARY We are seeking a Lead Behavioral Modeling Engineer to join Lattice Semiconductors FPGA Architecture & Design team. You will

Experience : 5+ Yrs Built and provisioned Windows servers (physical and virtual) — OS installation, role configuration (AD DS, DNS, DHCP, IIS), and post-build validation. • Deployed and managed VMware vSphere/ESXi environments across the enterprise —

Job Description Job Title Design Engineer – Medical Devices Department R&D – Medical Devices Location Vapi, Gujarat Reports To Manager / Senior Manager – Design & Development Job Purpose Meril Life Sciences is seeking a highly

L&T Technologies is looking to hire for SOC DV Lead role. Job Location : Bangalore Job Title : SoC DV Lead YEARS OF EXPERIENCE : 8+ Years JOB DESCRIPTION: Expertise in verifying SOC based on ARM and RISC

SOC RTL Design Verification Experience : 4 to 10 Years Location : Bangalore Key Responsibilities: • Verification of SOC RTL (This is a DV Req) : FW-HW co-verification at SOC level, good understanding of SOC boot flow,