Major Accountabilities: Manage QNX-based software development projects throughout the software development life cycle (SDLC), from requirements analysis and design to implementation, testing, and deployment. Optimize boot times and system performance for QNX-based embedded systems through bootloader
Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making that world a reality. Aptiv’s passionate
Software Build Engineer SHAPE THE FUTURE OF MOBILITY FROM DAY ONE. This position is part of our Advanced Safety & User Experience segment. Aptiv focuses on addressing the future needs of the auto industry through improved
SW Lead Developer – Autosar Classic Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making
SW Senior Developer – Autosar Classic Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making
Software Technical Manager – Autosar Classic Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making
Software Technical Manager – Autosar Classic Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making
Help shape the future of mobility. Imagine a world with zero vehicle accidents, zero vehicle emissions, and wireless vehicle connectivity all around us. Every day, we move closer to making that world a reality. Aptiv’s passionate
Job Details: Job Description: Intel is seeking a Design Verification Engineer for the Silicon Chassis team. In this role, you will independently own verification of interconnect and chassis IP blocks from planning through coverage closure, operating