Position : Verification Engineer Experience : 3 to 7 Years Location : Bangalore Notice Period : Immediate / 15 Days NP Must Have: Bachelor s/Master s degree in Electronics and Communication or VLSI Engineering. In-depth experience
Position : Design Engineer Experience : 3 7 Years Location : Bangalore Notice Period : immediate / 15 Days NP Skillset Required: Proficient in RTL Verification using SystemVerilog (SV) and UVM. Strong knowledge of FPGA Design
Job Title: FPGA Verification Engineer Experience:5+ years Job Location:Hyderabad, India Job Summary: We are looking for an experienced FPGA Verification Engineer with 5+ years of hands-on experience in FPGA verification, SystemVerilog, and UVM methodologies. The ideal