Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and synthesis
RTL Design Engineer (SDC Constraints) 𝗘𝘅𝗽𝗲𝗿𝗶𝗲𝗻𝗰𝗲: 𝟳+ 𝗬𝗲𝗮𝗿𝘀 𝗟𝗼𝗰𝗮𝘁𝗶𝗼𝗻: 𝗕𝗮𝗻𝗴𝗮𝗹𝗼𝗿𝗲 𝗪𝗼𝗿𝗸 𝗠𝗼𝗱𝗲: 𝗛𝘆𝗯𝗿𝗶𝗱 / 𝗥𝗲𝗺𝗼𝘁𝗲 𝗝𝗼𝗯 𝗢𝘃𝗲𝗿𝘃𝗶𝗲𝘄 We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
City : Sant Just Desvern State : Barcelona (ES-B) Country : Spain (ES) Requisition Number : 45095 Experiencia, cualificaciones y habilidades interpersonales, ¿tiene todo lo necesario para triunfar en esta oportunidad? Descúbralo a continuación. Overview We
Actualmente, tenemos un puesto vacante para un/a Data Architect que quiera unirse a nuestra compañía. Buscamos una persona con sólida trayectoría en ciencia de datos, capaz de liderar equipos o diseñar estrategias analíticas y guiar la
City : Sant Just DesvernState : Barcelona (ES-B)Country : Spain (ES)Requisition Number : 45095Overview: We are seeking a highly motivated and experienced Senior Data Engineer with strong expertise in data architecture, data engineering, data analysis, reporting, and