Job Description: Lead RTL design activities for complex ASIC/SoC development projects. Work closely with architecture and verification teams to define micro-architecture and implementation strategies. Develop high-quality RTL using Verilog/SystemVerilog. Drive block-level design, integration, lint, CDC, and synthesis
RTL Design Engineer (SDC Constraints) ๐๐ ๐ฝ๐ฒ๐ฟ๐ถ๐ฒ๐ป๐ฐ๐ฒ: ๐ณ+ ๐ฌ๐ฒ๐ฎ๐ฟ๐ ๐๐ผ๐ฐ๐ฎ๐๐ถ๐ผ๐ป: ๐๐ฎ๐ป๐ด๐ฎ๐น๐ผ๐ฟ๐ฒ ๐ช๐ผ๐ฟ๐ธ ๐ ๐ผ๐ฑ๐ฒ: ๐๐๐ฏ๐ฟ๐ถ๐ฑ / ๐ฅ๐ฒ๐บ๐ผ๐๐ฒ ๐๐ผ๐ฏ ๐ข๐๐ฒ๐ฟ๐๐ถ๐ฒ๐ We are looking for a highly skilled Senior RTL ASIC Design Engineer with strong hands-on experience in SDC Constraints.
City : Sant Just DesvernState : Barcelona (ES-B)Country : Spain (ES)Requisition Number : 45095Overview: We are seeking a highly motivated and experienced Senior Data Engineer with strong expertise in data architecture,โฏdata engineering, data analysis, reporting, and
City : Sant Just Desvern State : Barcelona (ES-B) Country : Spain (ES) Requisition Number : 45095 Overview We are seeking a highly motivated and experienced Senior Data Engineer with strong expertise in data architecture, data