Company Overview: NXP India - Global IT Support provides a proactive and predictive support framework via site IT managers, on-site support, service desk, and executive support, with the aspiration of creating a flawless user experience. We are
Responsibilities: o Act as a Functional Lead for an SOC, representing SOC_AMS team. o Guidance of analog & mixed signal architecture & integration of all analog IPs for assigned SOC. o Interpret analog/supply specifications of the
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the
Business Line Description: NXP is the world leader in secure connectivity solutions for automotive, industrial & IoT, mobile and communication infrastructure markets. NXP’s Automotive business unit offers sensor and processing technology that drives all aspects of the secure
Job description: The Digital Physical Design Engineer is responsible for a Timing Convergence (STA). The individual is responsible from writing timing constraints, interacting with different functions like IP, frontend, DFT, Verification to mature the timing constraints.
Job description Write verification documents such as verification plan and test plan. Define verification strategy according to design specification documents. Implement verification environments of IPs and SOC level. Work closely with digital designers/architects to solve suspected
Required Basic Qualification & Skills: Strong understanding of electrical circuit analysis, design, and test fundamentals Automation of Analog Characterization Setups using LabVIEW and Test Stand. Strong Debug and problem solving skills Bring up of Silicon &
The future starts here! Ready to join NXP in Technical Program Management? Be an integral member of a global, highly-experienced team in R&D that drives the planning and execution of advanced microcontroller and microprocessors. We are part
Key Responsibilities- FPGA-based Pre-Silicon validation Platform development for IP and Subsystems IP/SS Design porting and implementation for FPGA Development & bring-up of Pre-Silicon Validation platforms like Palladium/ZeBU/Veloce or FPGA for the IP/SOC Validation Development and execution
Job Description: Development of Calibre and Assura physical verification decks for cmos bulk, RF, bicmos and power mos technologies including DRC, LVS, LPE, supplemental and shape generation decks and scripts. Development and validation of other PV
About NXP: NXP is driving semiconductors innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Headquartered in The Netherlands, Eindhoven, NXP has a presence in more than 30 countries and India is one of the largest
Today’s complex SOCs have demanding performance goals. Meeting these goals is critical for success of these parts. The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed
Today’s complex SOCs have demanding performance goals. Meeting these goals is critical for success of these parts. The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed
Job Description The future starts here! Ready to join NXP in Technical Program Management? Be an integral member of a global, highly-experienced team in R&D that drives the planning and execution of advanced microcontroller and microprocessors. We
NXP Semiconductors N.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the
Skills required: Strong understanding of electrical circuit analysis, design, and test fundamentals Automation of Analog Characterization Setups using LabVIEW and Test Stand. Strong Debug and problem solving skills Bring up of Silicon & Analog Validation Platforms
Business Line Description: NXPs MCU/MPU Engineering (MME) team is a central engineering organization responsible for developing and delivering Systems-on-a-Chip (SoCs) for NXPs Automotive, Edge, and Radar Processing business lines. MMEs SoC Hardware Architecture team produces architectural solutions covering
Job Description The Digital Physical Design Engineer is responsible for a Timing Convergence (STA). The individual is responsible from writing timing constraints, interacting with different functions like IP, frontend, DFT, Verification to mature the timing constraints.